Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure.
Some FPGAs also include additional logic blocks with special purposes. For example, the Xilinx Virtex®-II FPGA includes blocks of Random Access Memory (RAM) and blocks implementing multiplier functions. (The Xilinx Virtex-II FPGA is described in detail in pages 33-75 of the “Virtex-II Platform FPGA Handbook”, published December 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference.)
Another special-purpose logic block included in the Virtex-II FPGA is a Digital Frequency Synthesizer (DFS) circuit. This circuit is described in pages 66 and 168-171 of the “Virtex-II Platform FPGA Handbook”, which pages are incorporated herein by reference.
The Virtex-II DFS circuit allows a multiplier (M) and a divider (D) to be applied to a first clock signal having a given input frequency to derive a second clock signal having a desired output frequency. The range of M is 1-4096, while the range of D is also 1-4096. Therefore, the maximum number of all M/D (M divided by D) combinations is 4096×4096=16,777,216.
Thus, to fully test the Virtex-II DFS circuit using conventional test methods would require that 16,777,216 different configuration data files (bitstreams) be created and stored, with each bitstream then being downloaded to each manufactured device and tested in operation in each device. Clearly, such a test procedure is prohibitively time-consuming. In fact, simply storing the bitstreams needed for such a test procedure would be quite impractical, as would providing the computer time necessary to generate the bitstreams and to test each manufactured device with each bitstream.
Therefore, it is desirable to provide methods for maximizing test coverage of a DFS circuit in a PLD without loading and testing every possible combination of M and D.